Various types of buses have been known from prior art for a long time. The present invention relates in particular to master-slave bus systems.
In many master-slave bus systems, the slave units of the system can be individually identified and addressed. A master unit is thus for example able to operate through a certain slave unit a component which is controlled by this slave unit, or to assign received messages to a specific slave unit—and thus also to a specific system component. In order to ensure such a functionality, the slave unit must have on the one hand a unique address; and on the other hand, this unique address and the assignment of the slave unit to a system component or its position in the bus system of the master unit must be known.
This is conventionally achieved for example with a bus addressing or orientation phase which is performed during the initializing of a bus system. During this phase, system addresses are assigned for example in a specific sequence to the slave units, or the master unit is given the opportunity to query sequentially stored device identifiers of individual slave units at different positions. For example, an address assignment to the slave units is performed manually, wherein the slaves which are present in a defined order of succession are manually connected to the bus system individually one after another, or they are released for addressing individually by means of a manually operated switch: Since only one defined, manually selectable slave unit is connected to the bus line or released for addressing, the master unit can by issuing one broadcast command—which is in fact directed to all slave units depending on the bus system—assign a unique address to this individual slave unit. Due to this defined sequence in which the slave units are addressed, the master unit knows after the assignment of the address also the relative position of the individual units in the system.
Similar manual processes are not only time consuming and tedious, but they are also error-prone because a human user must be necessarily involved.
An automated—and therefore faster—addressing system is proposed in DE 103 36 301 A1. The addressing procedure is suitable for a master-slave bus system which is provided with a bus line having a beginning and end that is connected with the master unit. In addition, the bus line is continuously looped through the slave units. Each slave unit is provided with a switch for interrupting the bus line. In order to initialize the addressing procedure, an address assignment signal is provided at one clock input, which induces all slave units to interrupt the bus line and to assume the shift register state. The master unit then transfers sequentially the addresses to be assigned to the first slave unit; the first slave unit then shifts the addresses again one after another to the successive slave units, etc. When the first address arrives in this manner to the master unit, the master unit inputs an address acceptance signal at the clock input, after which all slave unit accept their current addresses and their switches are closed.
With this method, the bus line is interrupted during the course of the address assignment process, so that the master unit must address the slave units through one clock input.
In addition, the procedure can be used only for systems which are provided with a circular bus line and which also enable communication from one slave to another slave.
Another automatic addressing procedure is indicated in DE 199 35 192 A1. This procedure is in particular suitable for master-slave bus systems in which the slave units are provided with a unique device identifier that is preset at the factory. During the initialization of the bus system, a static activation signal is provided from a master unit through the slave units which are looped through the address line. The signal will reach only the first slave unit, which is then set to an “activated state” in which addressing is possible. After that the master sends a subscriber address for the activated slave unit and in response to this, the slave unit will send its device identifier to the master. If the identifier is identical to the expected identifier, the slave unit accepts the address. An internal slave logical unit than switches the activation signal through to the address line output of the slave unit, so that the activation signal will reach the next slave. An addressed slave is then no longer accessible for address data.
This solution is suitable for a bus system which had unidirectional lines and slave units provided with factory-preset IDs or device identifiers. After the initialization of the system, addressing is no longer possible.
EP 1 320 222 A1 relates to a bus system which has several master and slave units in which a bus line is looped through the system. A switch in the modules can interrupt the bus line. An addressing procedure can be performed prior to the start of a normal operation, so that the switches are closed sequentially and addresses are assigned to the associated slaves.
Similar procedures are also described in DE 44, 28 502 A1, DE 102 33 978 A1, DE 44 04 962 C2, DE 10 2005 0014 A1 and DE 10 2006 029 997 A1.